Chapter 12 Pierce Oscillator (S12XOSCLCPV2)
MC9S12XE-Family Reference Manual , Rev. 1.19
498
Freescale Semiconductor
12.1.3
Block Diagram
shows a block diagram of the XOSC.
Figure 12-1. XOSC Block Diagram
12.2
External Signal Description
This section lists and describes the signals that connect off chip
12.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (V
DDPLL
) and ground (V
SSPLL
) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
12.2.2
EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
EXTAL
XTAL
Gain Control
V
DDPLL
= 1.8 V
Rf
OSCCLK
Monitor_Failure
Clock
Monitor
Peak
Detector
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
