Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
568
Freescale Semiconductor
Figure 14-71. 16-Bit Pulse Accumulators Block Diagram
Figure 14-72. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
Edge Detector
P7
P0
Bus Clock
Divide by 64
Clock Select
CLK0
CLK1
4:1 MUX
TIMCLK (Timer Clock)
P
A
CLK
P
A
CLK / 256
P
A
CLK / 65536
Prescaled Clock
(PCLK)
Interrupt
MUX
(PAMOD)
Edge Detector
PACA
Delay Counter
Interrupt
PACB
8-Bit PAC3
(PACN3)
8-Bit PAC2
(PACN2)
8-Bit PAC1
(PACN1)
8-Bit PAC0
(PACN0)
Px
Edge
Delay
16-Bit Main Timer
TCx Input
TCxH I.C.
BUFEN
•
LATQ
•
TFMOD
Set CxF
Detector
Counter
Capture Register
Holding Register
Interrupt
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
