Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
606
Freescale Semiconductor
Figure 16-2. CAN System
16.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
16.3.1
Module Memory Map
gives an overview on all registers and their individual bits in the MSCAN memory map. The
register address
results from the addition of
base address
and
address offset
. The
base address
is
determined at the MCU level and can be found in the MCU memory map description. The
address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
The detailed register descriptions follow in the order they appear in the register map.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
CANCTL0
R
RXFRM
RXACT
CSWAI
SYNCH
TIME
WUPE
SLPRQ
INITRQ
W
0x0001
CANCTL1
R
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SLPAK
INITAK
W
= Unimplemented or Reserved
u = Unaffected
Figure 16-3. MSCAN Register Summary
CAN Bus
CAN Controller
(MSCAN)
Transceiver
CAN node 1
CAN node 2
CAN node n
CAN_L
CAN_H
MCU
TXCAN
RXCAN
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
