Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
653
After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode
was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message
aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it
continues counting the 128 occurrences of 11 consecutive recessive bits.
16.4.5.5
MSCAN Initialization Mode
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization
to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from
fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
NOTE
The user is responsible for ensuring that the MSCAN is not active when
initialization mode is entered. The recommended procedure is to bring the
MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the
INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going
message can cause an error condition and can impact other CAN bus
devices.
In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode
is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ,
CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the
configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR,
CANIDMR message filters. See
Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)
,” for a
detailed description of the initialization mode.
Figure 16-46. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 16-46., “Initialization Request/Acknowledge Cycle
SYNC
SYNC
Bus Clock Domain
CAN Clock Domain
CPU
Init Request
INIT
Flag
INITAK
Flag
INITRQ
sync.
INITAK
sync.
INITRQ
INITAK
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Commission,
BGA-packaged
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