Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
716
Freescale Semiconductor
Figure 19-20. PWM Left Aligned Output Waveform
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
•
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
•
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
•
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
As an example of a left aligned output, consider the following case:
Clock Source = E, where E = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
The output waveform generated is shown in
Figure 19-21. PWM Left Aligned Output Example Waveform
19.4.2.6
Center Aligned Outputs
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the
corresponding PWM output will be center aligned.
PWMDTYx
Period = PWMPERx
PPOLx = 0
PPOLx = 1
Period = 400 ns
E = 100 ns
Duty Cycle = 75%
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
