Chapter 20 Serial Communication Interface (S12SCIV5)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
731
20.3.2.5
SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 20-7. SCIACR1 Field Descriptions
Field
Description
7
RSEDGIE
Receive Input Active Edge Interrupt Enable
— RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1
BERRIE
Bit Error Interrupt Enable
— BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
0
BKDIE
Break Detect Interrupt Enable
— BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
0
0
0
0
BERRM1
BERRM0
BKDFE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-8. SCI Alternative Control Register 2 (SCIACR2)
Table 20-8. SCIACR2 Field Descriptions
Field
Description
2:1
BERRM[1:0]
Bit Error Mode
— Those two bits determines the functionality of the bit error detect feature. See
.
0
BKDFE
Break Detect Feature Enable
— BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
Table 20-9. Bit Error Mode Coding
BERRM1
BERRM0
Function
0
0
Bit error detect circuit is disabled
0
1
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to
)
1
0
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
