Chapter 23 Voltage Regulator (S12VREGL3V3V1)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
829
23.4.11.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage V
DDA
. Whenever V
DDA
drops below level V
LVIA,
the
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
DDA
rises above level V
LVID
. An
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
NOTE
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG_3V3.
23.4.11.2 HTI - High Temperature Interrupt
In FPM VREG monitors the die temperature T
DIE
. Whenever T
DIE
exceeds level T
HTIA
the status bit
HTDS is set to 1. Vice versa, HTDS is reset to 0 when T
DIE
get below level T
HTID
. An interrupt, indicated
by flag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.
NOTE
On entering the Reduced Power Mode the HTIF is not cleared by the VREG.
23.4.11.3 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
Table 23-13. Interrupt Vectors
Interrupt Source
Local Enable
Low-voltage interrupt (LVI)
LVIE = 1; available only in Full Performance
Mode
High Temperature Interrupt (HTI)
HTIE=1;
available only in Full Performance Mode
Autonomous periodical interrupt (API)
APIE = 1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
