MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
832
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase).
24.1.1
Glossary
Buffer RAM
— The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Command Write Sequence
— An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory
— The D-Flash memory constitutes the nonvolatile memory store required for EEE.
Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile
memory space for applications.
D-Flash Sector
— The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
EEE (Emulated EEPROM)
— A method to emulate the small sector size features and endurance
characteristics associated with an EEPROM.
EEE IFR
— Nonvolatile information register located in the D-Flash block that contains data required to
partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map
by setting the EEEIFRON bit in the MMCCTL1 register.
NVM Command Mode
— An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase
— An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight
ECC bits for single bit fault correction and double bit fault detection within the phrase.
P-Flash Memory
— The P-Flash memory constitutes the main nonvolatile memory store for applications.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
