Chapter 1 Device Overview MC9S12XE-Family
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
85
the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data
is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without
impacting the CPU and FTM commands can be executed.
1.6.3.3
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
I/O Pins
Refer to the PIM block description for reset configurations of all peripheral module ports.
1.6.3.5
Memory
The RAM arrays are not initialized out of reset.
1.6.3.6
COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash register FOPT. See
and
for coding. The FOPT register is
loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP
reset.
Table 1-15. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000
111
001
110
010
101
011
100
100
011
101
010
110
001
111
000
Table 1-16. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
COPCTL Register
1
0
0
1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
