where K is a constant pertaining to the particular part. K can be determined by measuring
P
D
(at equilibrium) for an known T
A
. Using this value of K, the values of P
D
and T
J
can
be obtained by solving the above equations iteratively for any value of T
A
.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 11. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
20
MHz
J2
SWD_CLK cycle period
1/J1
—
ns
J3
SWD_CLK clock pulse width
• Serial wire debug
20
—
ns
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
3
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
35
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
J4
J4
SWD_CLK (input)
Figure 13. Serial wire clock input timing
Peripheral operating requirements and behaviors
KE02 Sub-Family Data Sheet, Rev4, 10/2014.
20
Freescale Semiconductor, Inc.
