Freescale Semiconductor *KE02 Series, Technical Data Manual

Page 1: ...med for up to 20 MHz system clock Internal 1 kHz low power oscillator LPO System peripherals Power management module PMC with three power modes Run Wait Stop Low voltage detection LVD with reset or in...

Page 2: ...hannel periodic interrupt timer PIT One real time clock RTC Communication interfaces Two SPI modules SPI Up to three UART modules UART One I2C module I2C Package options 64 pin QFP LQFP 44 pin LQFP 32...

Page 3: ...1 Control timing 16 5 2 2 FTM module timing 17 5 3 Thermal specifications 18 5 3 1 Thermal operating requirements 18 5 3 2 Thermal characteristics 18 6 Peripheral operating requirements and behaviors...

Page 4: ...pecific part you have received 2 2 Format Part numbers for this device have the following format Q KE A FFF R T PP CC N 2 3 Fields This table lists the possible values for each field in the part numbe...

Page 5: ...n the tables where appropriate Table 1 Parameter classifications P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design cha...

Page 6: ...rge voltage human body model 6000 6000 V 1 VCDM Electrostatic discharge voltage charged device model 500 500 V 2 ILAT Latch up current at ambient temperature of 125 C 100 100 mA 3 1 Determined accordi...

Page 7: ...vel for instance either VSS or VDD or the programmable pullup resistor associated with the pin is enabled Table 2 Voltage and current operating ratings Symbol Description Min Max Unit VDD Digital supp...

Page 8: ...VIL P Input low voltage All digital inputs 4 5 VDD 5 5 V 0 35 VDD V 2 7 VDD 4 5 V 0 30 VDD Vhys C Input hysteresi s All digital inputs 0 06 VDD mV IIn P Input leakage current Per pin pins in high imp...

Page 9: ...consumption Table 4 LVD and POR specification Symbol C Description Min Typ Max Unit VPOR D POR re arm voltage1 1 5 1 75 2 0 V VLVDH C Falling low voltage detect threshold high range LVDV 1 2 4 2 4 3...

Page 10: ...D VOH Vs IOH standard drive strength VDD 5 V IOH mA VDD VOH V Figure 2 Typical VDD VOH Vs IOH standard drive strength VDD 3 V Nonswitching electrical specifications KE02 Sub Family Data Sheet Rev4 10...

Page 11: ...l VDD VOH Vs IOH high drive strength VDD 5 V IOH mA VDD VOH V Figure 4 Typical VDD VOH Vs IOH high drive strength VDD 3 V Nonswitching electrical specifications KE02 Sub Family Data Sheet Rev4 10 2014...

Page 12: ...l VOL Vs IOL standard drive strength VDD 5 V IOL mA VOL V Figure 6 Typical VOL Vs IOL standard drive strength VDD 3 V Nonswitching electrical specifications KE02 Sub Family Data Sheet Rev4 10 2014 12...

Page 13: ...pical VOL Vs IOL high drive strength VDD 5 V IOL mA VOL V Figure 8 Typical VOL Vs IOL high drive strength VDD 3 V Nonswitching electrical specifications KE02 Sub Family Data Sheet Rev4 10 2014 Freesca...

Page 14: ...supply current FBE mode all modules clocks enabled run from RAM RIDD 20 20 MHz 5 9 14 8 mA 40 to 105 C C 10 10 MHz 5 2 1 1 MHz 1 45 P 20 20 MHz 3 8 8 11 8 C 10 10 MHz 5 1 1 1 MHz 1 4 P Run supply cur...

Page 15: ...ibility EMC performance is highly dependent on the environment in which the MCU resides Board design and layout circuit topology choices location and characteristics of external components as well as...

Page 16: ...measured emission rounded up to the next whole number from among the measured orientations in each frequency range 2 VDD 5 0 V TA 25 C fOSC 10 MHz crystal fBUS 20 MHz 3 Specified according to Annex D...

Page 17: ...et timing tIHIL KBIPx tILIH IRQ KBIPx Figure 10 KBIPx timing 5 2 2 FTM module timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be u...

Page 18: ...ssipation in on chip logic and voltage regulator circuits and it is user determined rather than being controlled by the MCU design To take PI O into account in power calculations determine the differe...

Page 19: ...ard JESD51 7 horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Thermal r...

Page 20: ...Max Unit Operating voltage 2 7 5 5 V J1 SWD_CLK frequency of operation Serial wire debug 0 20 MHz J2 SWD_CLK cycle period 1 J1 ns J3 SWD_CLK clock pulse width Serial wire debug 20 ns J4 SWD_CLK rise a...

Page 21: ...range RANGE 0 flo 31 25 32 768 39 0625 kHz C High range RANGE 1 fhi 4 20 MHz 2 D Load capacitors C1 C2 See Note2 3 D Feedback resistor Low Frequency Low Power Mode3 RF M Low Frequency High Gain Mode 1...

Page 22: ...C fdco_ft 1 1 14 C FLL acquisition time4 6 tAcquire 2 ms 15 C Long term jitter of DCO output clock averaged over 2 ms interval 7 CJitter 0 02 0 2 fdco 1 Data in Typical column was characterized at 5...

Page 23: ...erify Flash Block tRD1BLK 16913 tcyc D Erase Verify EEPROM Block tRD1BLK 810 tcyc D Erase Verify Flash Section tRD1SEC 484 tcyc D Erase Verify EEPROM Section tDRD1SEC 555 tcyc D Read Once tRDONCE 450...

Page 24: ...typical fNVMOP and maximum fNVMBUS 3 Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging 4 tcyc 1 fNVMBUS Program and erase operations do not require any special power sources ot...

Page 25: ...erwise stated Typical values are for reference only and are not tested in production ADC SAR ENGINE SIMPLIFIED CHANNEL SELECT CIRCUIT SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input p...

Page 26: ...cycles Long sample ADLSMP 1 40 Sample time Short sample ADLSMP 0 T tADS 3 5 ADCK cycles Long sample ADLSMP 1 23 5 Total unadjusted Error2 12 bit mode T ETUE 5 0 LSB3 10 bit mode P 1 5 2 0 8 bit mode...

Page 27: ...omparator electrical specifications C Characteristic Symbol Min Typical Max Unit D Supply voltage VDDA 2 7 5 5 V T Supply current Operation mode IDDA 10 20 A D Analog input voltage VAIN VSS 0 3 VDDA V...

Page 28: ...SCK Clock SPSCK high or low time tBus 30 1024 x tBus ns 6 tSU Data setup time inputs 8 ns 7 tHI Data hold time inputs 8 ns 8 tv Data valid after SPSCK edge 25 ns 9 tHO Data hold time outputs 20 ns 10...

Page 29: ...ontrol timing 2 tSPSCK SPSCK period 4 x tBus ns tBus 1 fBus 3 tLead Enable lead time 1 tBus 4 tLag Enable lag time 1 tBus 5 tWSPSCK Clock SPSCK high or low time tBus 30 ns 6 tSU Data setup time inputs...

Page 30: ...timing CPHA 0 2 6 7 MSB IN BIT 6 1 MSB OUT SLAVE LSB OUT 5 5 10 12 13 3 12 13 4 SLAVE 8 9 see note INPUT CPOL 0 SPSCK SPSCK CPOL 1 SS INPUT INPUT MOSI INPUT MISO OUTPUT NOTE Not defined 11 LSB IN BIT...

Page 31: ...esponsible for selecting which ALT functionality is available on each pin Table 19 Pin availability by package pin count Pin Number Lowest Priority Highest 64 QFP LQFP 44 LQFP 32 LQFP Port Pin Alt 1 A...

Page 32: ...2 KBI0_P6 SPI0_SCK FTM0_CH0 ADC0_SE6 33 23 17 PTB1 KBI0_P5 UART0_TX ADC0_SE5 34 24 18 PTB0 KBI0_P4 UART0_RX ADC0_SE4 35 PTF3 36 PTF2 37 25 19 PTA7 FTM2_FLT2 ACMP1_IN1 ADC0_SE3 38 26 20 PTA6 FTM2_FLT1...

Page 33: ...lly connected 4 This is a true open drain pin when operated as output Note When an alternative function is first enabled it is possible to get a spurious edge to the module User software must clear an...

Page 34: ...2 11 13 14 15 16 39 40 38 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 58 60 61 62 63 64 Figure 21 64 pin QFP LQFP packages PTB1 PTB2 PTC3 2 True open drain pins PTB0 PTB3 PTA7 PT...

Page 35: ...A Updated the features of OSC ICS UART KBI and ADC in the front page Updated ILAT and VCDM in the ESD handling ratings Added VIN and removed VDIO VAIO in the Voltage and current operating ratings Upda...

Page 36: ...ithout limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual perfor...

Page 37: ...Distributor Click to View Pricing Inventory Delivery Lifecycle Information Freescale Semiconductor MKE02Z16VLC2 MKE02Z32VLC2 MKE02Z16VLD2 MKE02Z32VLD2 MKE02Z32VQH2 MKE02Z64VLC2 MKE02Z64VLD2 MKE02Z64V...