<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6
7
MSB IN
2
BIT 6 . . . 1
MASTER MSB OUT
2
MASTER LSB OUT
5
5
8
10
11
PORT DATA
PORT DATA
3
10
11
4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
LSB IN
BIT 6 . . . 1
Figure 18. SPI master mode timing (CPHA=1)
Table 18. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
f
op
Frequency of operation
0
f
Bus
/4
Hz
f
Bus
is the bus clock as
.
2
t
SPSCK
SPSCK period
4 x t
Bus
—
ns
t
Bus
= 1/f
Bus
3
t
Lead
Enable lead time
1
—
t
Bus
—
4
t
Lag
Enable lag time
1
—
t
Bus
—
5
t
WSPSCK
Clock (SPSCK) high or low time
t
Bus
- 30
—
ns
—
6
t
SU
Data setup time (inputs)
15
—
ns
—
7
t
HI
Data hold time (inputs)
25
—
ns
—
8
t
a
Slave access time
—
t
Bus
ns
Time to data active from
high-impedance state
9
t
dis
Slave MISO disable time
—
t
Bus
ns
Hold time to high-
impedance state
10
t
v
Data valid (after SPSCK edge)
—
25
ns
—
11
t
HO
Data hold time (outputs)
0
—
ns
—
12
t
RI
Rise time input
—
t
Bus
- 25
ns
—
t
FI
Fall time input
13
t
RO
Rise time output
—
25
ns
—
t
FO
Fall time output
Peripheral operating requirements and behaviors
KE02 Sub-Family Data Sheet, Rev4, 10/2014.
Freescale Semiconductor, Inc.
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