Freescale Semiconductor *KE02 Series, Technical Data Manual

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

(continued)

Num

C

Characteristic

Symbol

Min

Typical

1

Max

Unit

D

Series resistor -

High

Frequency,

High-Gain Mode

4 MHz

—

0

—

kΩ

D

8 MHz

—

0

—

kΩ

D

16 MHz

—

0

—

kΩ

6

C

Crystal start-up

time low range

= 32.768 kHz

crystal; High

range = 20 MHz

crystal

4

,

5

Low range, low power

t

CSTL

—

1000

—

ms

C

Low range, high gain

—

800

—

ms

C

High range, low power

t

CSTH

—

3

—

ms

C

High range, high gain

—

1.5

—

ms

7

T

Internal reference start-up time

t

IRST

—

20

50

µs

8

P

Internal reference clock (IRC) frequency trim

range

f

int_t

31.25

—

39.0625

kHz

9

P

Internal

reference clock

frequency,

factory trimmed

,

T = 25 °C, V

DD

 = 5 V

f

int_ft

—

31.25

—

kHz

10

P

DCO output

frequency range

FLL reference = fint_t, flo,

or fhi/RDIV

f

dco

16

—

20

MHz

11

P

Factory trimmed

internal

oscillator
accuracy

T = 25 °C, V

DD

 = 5 V

Δ

f

int_ft

-0.5

—

0.5

%

12

C

Deviation of IRC

over

temperature

when trimmed

at T = 25 °C,

V

DD

 = 5 V

Over temperature range

from -40 °C to 105°C

Δ

f

int_t

-1

—

0.5

%

Over temperature range

from 0 °C to 105°C

Δ

f

int_t

-0.5

—

0.5

13

C

Frequency

accuracy of

DCO output

using factory

trim value

Over temperature range

from -40 °C to 105°C

Δ

f

dco_ft

-1.5

—

1

%

Over temperature range

from 0 °C to 105°C

Δ

f

dco_ft

-1

—

1

14

C

FLL acquisition time

4

,

6

t

Acquire

—

—

2

ms

15

C

Long term jitter of DCO output clock

(averaged over 2 ms interval)

7

C

Jitter

—

0.02

0.2

%f

dco

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C

1

,C

2

), feedback resistor (R

F

) and series resistor (R

S

) are incorporated internally when RANGE = HGO =

0.

4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.

7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

DD

 and V

SS

 and variation in crystal oscillator frequency increase the C

Jitter

 percentage

for a given interval.

Peripheral operating requirements and behaviors

KE02 Sub-Family Data Sheet, Rev4, 10/2014.

22

Freescale Semiconductor, Inc.