9.3 SWD status and control registers
Through the ARM Debug Access Port (DAP), the debugger has access to the status and
control elements, implemented as registers on the DAP bus as shown in
. These
registers provide additional control and status for low power mode recovery and typical
run-control scenarios. The status register bits also provide a means for the debugger to
get updated status of the core without having to initiate a bus transaction across the
crossbar switch, thus remaining less intrusive during a debug session.
It is important to note that these DAP control and status registers are not memory mapped
within the system memory map and are only accessible via the Debug Access Port using
SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers
shown in the table below.
Table 9-2. MDM-AP register summary
Address
Register
Description
0x0100_0000
Status
0x0100_0004
Control
0x0100_00FC
IDR
Read-only identification register that
always reads as 0x001C_0020
SWD status and control registers
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
116
Freescale Semiconductor, Inc.
