10.4.6 Timer Modules
Table 10-8. TPM0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
EXTCLK
External clock. FTM external clock can be selected to drive the
FTM counter.
I
TPM0_CH[5:0]
CHn
FTM channel (n), where n can be 7-0
I/O
Table 10-9. TPM1 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment the
TPM counter on every rising edge synchronized to the counter
clock.
I
TPM1_CH[1:0]
TPM_CHn
TPM channel (n = 1 to 0)
I/O
Table 10-10. LPTMR0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
LPTMR0_ALT[2:1]
LPTMR_ALT
n
Pulse Counter Input pin
I
10.4.7 Communication interfaces
Table 10-11. SPI0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI0_MISO
MISO
Master Data In, Slave Data Out
I/O
SPI0_MOSI
MOSI
Master Data Out, Slave Data In
I/O
SPI0_SCLK
SPSCK
SPI Serial Clock
I/O
SPI0_PCS0
SS
Slave Select
I/O
Table 10-12. I
2
C0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
I2C0_SCL
SCL
Bidirectional serial clock line of the I
2
C system.
I/O
I2C0_SDA
SDA
Bidirectional serial data line of the I
2
C system.
I/O
Chapter 10 Signal Multiplexing and Signal Descriptions
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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