• Highest: V
LVW4
• Two mid-levels: V
LVW3
and V
LVW2
• Lowest: V
LVW1
14.4 I/O retention
When in VLLS modes, the I/O states are held on a wakeup event (with the exception of
wakeup by reset event) until the wakeup has been acknowledged via a write to the
ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default
to their reset state. In this case, no write to the ACKISO is needed.
14.5 Memory map and register descriptions
PMC register details follow.
NOTE
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details. For
more information about the types of reset on this chip, refer to
the Reset section details.
The PMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
PMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_D000
Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
8
R/W
10h
4007_D001
Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
8
R/W
00h
4007_D002 Regulator Status And Control register (PMC_REGSC)
8
R/W
04h
Chapter 14 Power Management Controller (PMC)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
183
