In addition, there are two signals formed by the MTB_DWT module and driven to the
MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can
be configured using the trace watchpoints to define programmable addresses and data
values to affect the program trace recording state.
18.3 Memory map and register definition
The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB
address space for their programming models. For each address space, there are a variety
of control and configurable registers near the base address, followed by a large unused
address space and finally a set of CoreSight registers to support dynamic determination of
the debug configuration for the device.
Accesses to the programming model follow standard ARM conventions. Taken from the
ARM CoreSight Micro Trace Buffer documentation, these are:
• Do not attempt to access reserved or unused address locations. Attempting to access
these locations can result in UNPREDICTABLE behavior.
• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN
reset values are not programmed prior to enabling trace.
• Unless otherwise stated in the accompanying text:
• Do not modify reserved register bits
• Ignore reserved register bits on reads
• All register bits are reset to a logic 0 by a system or power-on reset
• Use only word size, 32-bit, transactions to access all registers
18.3.1 MTB_RAM Memory Map
MTB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F000_0000 MTB Position Register (MTB_POSITION)
32
R/W
Undefined
F000_0004 MTB Master Register (MTB_MASTER)
32
R/W
F000_0008 MTB Flow Register (MTB_FLOW)
32
R/W
Undefined
F000_000C MTB Base Register (MTB_BASE)
32
R
Undefined
F000_0F00 Integration Mode Control Register (MTB_MODECTRL)
32
R
0000_0000h
Table continues on the next page...
Memory map and register definition
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
228
Freescale Semiconductor, Inc.
