25.3.2 ADC Configuration Register 1 (ADCx_CFG1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock
divide, and configuration for low power or long sample time.
Address: 4003_B000h base + 8h offset = 4003_B008h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCx_CFG1 field descriptions
Field
Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
ADLPC
Low-Power Configuration
Controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
0
Normal power configuration.
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
6–5
ADIV
Clock Divide Select
Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00
The divide ratio is 1 and the clock rate is input clock.
01
The divide ratio is 2 and the clock rate is (input clock)/2.
10
The divide ratio is 4 and the clock rate is (input clock)/4.
11
The divide ratio is 8 and the clock rate is (input clock)/8.
4
ADLSMP
Sample Time Configuration
Selects between different sample times based on the conversion mode selected. This field adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power
consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample
time.
Table continues on the next page...
Chapter 25 Analog-to-Digital Converter (ADC)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
347
