29.4.3 Slave mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register 1 is clear.
• SPSCK
In slave mode, SPSCK is the SPI clock input from the master.
• MISO, MOSI pin
In slave mode, the function of the serial data output pin (MISO) and serial data input
pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register
2.
• SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of
the slave SPI must be low. SS must remain low until the transmission is complete. If
SS goes high, the SPI is forced into an idle state.
The SS input also controls the serial data output pin. If SS is high (not selected), the
serial data output pin is high impedance. If SS is low, the first bit in the SPI Data
Register is driven out of the serial data output pin. Also, if the slave is not selected
(SS is high), then the SPSCK input is ignored and no internal shifting of the SPI shift
register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of
only receiving SPI data in a slave mode. For these simpler devices, there is no serial
data out pin.
Note
When peripherals with duplex capability are used, take care not
to simultaneously enable two receivers whose serial outputs
drive the same system slave's serial data output line.
As long as no more than one slave device drives the system slave's serial data output line,
it is possible for several slaves to receive the same transmission from a master, although
the master would not receive return information from all of the receiving slaves.
If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK
input cause the data at the serial data input pin to be latched. Even numbered edges cause
the value previously latched from the serial data input pin to shift into the LSB or MSB
of the SPI shift register, depending on the LSBFE bit.
Chapter 29 Serial Peripheral Interface (SPI)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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