M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
S
T
O
P
S
T
A
R
T
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
BAUD
IRQ
IRQ Requests
Figure 31-2. UART receiver block diagram
31.2 Register definition
The UART includes registers to control baud rate, select UART options, report UART
status, and for transmit/receive data. Accesses to address outside the valid memory map
will generate a bus error.
UART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A000 UART Baud Rate Register High (UART0_BDH)
8
R/W
00h
4006_A001 UART Baud Rate Register Low (UART0_BDL)
8
R/W
04h
4006_A002 UART Control Register 1 (UART0_C1)
8
R/W
00h
4006_A003 UART Control Register 2 (UART0_C2)
8
R/W
00h
4006_A004 UART Status Register 1 (UART0_S1)
8
R/W
C0h
4006_A005 UART Status Register 2 (UART0_S2)
8
R/W
00h
4006_A006 UART Control Register 3 (UART0_C3)
8
R/W
00h
4006_A007 UART Data Register (UART0_D)
8
R/W
00h
4006_A008 UART Match Address Registers 1 (UART0_MA1)
8
R/W
00h
4006_A009 UART Match Address Registers 2 (UART0_MA2)
8
R/W
00h
Table continues on the next page...
Register definition
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
498
Freescale Semiconductor, Inc.
