Table 5-1. Clock summary (continued)
Clock name
Run mode
clock frequency
VLPR mode
clock frequency
Clock source
Clock is disabled
when…
Flash clock
Up to 24 MHz
Up to 1 MHz in BLPE
Up to 800 kHz in BLPI
MCGOUTCLK clock
divider
In all stop modes
except for partial
STOP2 mode
Internal reference
(MCGIRCLK)
30–40 kHz Slow IRC
or 4 MHz Fast IRC
4 MHz Fast IRC only
MCG
MCG_C1[IRCLKEN]
cleared,
Stop/VLPS mode and
MCG_C1[IREFSTEN]
cleared, or
VLLS mode
External reference
(OSCERCLK)
Up to 48 MHz (bypass),
30–40 kHz
Up to 16 MHz (bypass),
30–40 kHz
System OSC
System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
or VLLS0 and oscillator
not in external clock
mode.
External reference
32kHz
(ERCLK32K)
30–40 kHz
30–40 kHz
System OSC
System OSC's
OSC_CR[ERCLKEN]
cleared
or VLLS0 and oscillator
not in external clock
mode.
1 kHz
1 kHz
PMC
in VLLS0
Up to 48 MHz
Up to 8 MHz
MCGIRCLK,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[TPMSRC
]=00 or selected clock
source disabled.
Up to 48 MHz
Up to 8 MHz
MCGIRCLK,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[UART0SR
C]=00 or selected clock
source disabled.
1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 800 kHz if executing from flash.
5.5 Internal clocking requirements
The clock dividers are programmed via the CLKDIV registers of the SIM module. The
following requirements must be met when configuring the clocks for this device:
Internal clocking requirements
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
88
Freescale Semiconductor, Inc.
