The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset)
to occur.
6.2.3.5 Early Chip Reset
The Early Chip Reset asserts on all reset sources. It resets only the flash memory module.
It negates before flash memory initialization begins ("earlier" than when the Chip Reset
negates).
6.2.3.6 Chip Reset
Chip Reset asserts on all reset sources and only negates after flash initialization has
completed and the RESET_b pin has also negated. It resets the remaining modules (the
modules not reset by other reset types).
6.2.4 RESET_b pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin,
the RESET_b pin is driven low by the MCU for at least 128 bus clock cycles and until
flash initialization has completed.
After flash initialization has completed, the RESET_b pin is released, and the internal
Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin
asserted externally delays the negation of the internal Chip Reset.
The RESET_b pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG]
option bit to 0 (See
). When this option is selected, there could be a short period
of contention during a POR ramp where the device drives the pinout low prior to
establishing the setting of this option and releasing the RESET function on the pin.
6.2.5 Debug resets
The following sections detail the debug resets available on the device.
Reset
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
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Freescale Semiconductor, Inc.
