• It can be a free-running counter or modulo counter
• The counting can be up or up-down
• Includes 2 channels that can be configured for input capture, output compare, or
edge-aligned PWM mode
• In input capture mode the capture can occur on rising edges, falling edges or
both edges
• In output compare mode the output signal can be set, cleared, pulsed, or toggled
on match
• All channels can be configured for center-aligned PWM mode
• Support the generation of an interrupt per channel
• Support the generation of an interrupt when the counter overflows
• Support selectable trigger input to optionally reset or cause the counter to start
incrementing.
• The counter can also optionally stop incrementing on counter overflow
• Support the generation of hardware triggers when the counter overflows and per
channel
27.1.3 Modes of Operation
During debug mode, the TPM can can be configured to temporarily pause all counting
until the core returns to normal user operating mode or to operate normally. When the
counter is paused, trigger inputs and input capture events are ignored.
During doze mode, the TPM can be configured to operate normally or to pause all
counting for the duration of doze mode. When the counter is paused, trigger inputs and
input capture events are ignored.
During stop mode, the TPM counter clock can remain functional and the TPM can
generate an asynchronous interrupt to exit the MCU from stop mode.
27.1.4 Block Diagram
The TPM uses one input/output (I/O) pin per channel, CHn (TPM channel (n)) where n is
the channel number.
Introduction
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
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Freescale Semiconductor, Inc.
