0
0
0
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
TOF bit
set TOF bit
set TOF bit
period of counting = 2 x MOD x period of timer module counter clock
MOD = 0x0004
period of timer module counter clock
Timer module counter
Figure 27-37. Example of Up-Down Counting
27.4.3.3 Counter Reset
Any write to CNT resets the TPM counter and the channel outputs to their initial values
(except for channels in output compare mode).
27.4.4 Input Capture Mode
The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and
(ELSnB:ELSnA ≠ 0:0).
When a selected edge occurs on the channel input, the current value of the TPM counter
is captured into the CnV register, at the same time the CHnF bit is set and the channel
interrupt is generated if enabled by CHnIE = 1 (see the following figure).
When a channel is configured for input capture, the TPM_CHn pin is an edge-sensitive
input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-
capture event. Note that the maximum frequency for the channel input signal to be
detected correctly is counter clock divided by 4, which is required to meet Nyquist
criteria for signal sampling.
Writes to the CnV register are ignored in input capture mode.
Chapter 27 Timer/PWM Module (TPM)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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