channel (n) input
synchronizer
edge
detector
was falling
edge selected?
was rising
edge selected?
rising edge
falling edge
0
1
1
0
0
0
CnV
D
Q
CLK
D
Q
CLK
channel (n) interrupt
CHnIE
CHnF
timer module clock
timer module counter
Figure 27-38. Input capture mode
The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs
on the channel input.
27.4.5 Output Compare Mode
The output compare mode is selected when (CPWMS = 0), and (MSnB:MSnA = X:1).
In output compare mode, the TPM can generate timed pulses with programmable
position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared or
toggled if MSnB is clear. If MSnB is set then the channel (n) output is pulsed high or low
for as long as the counter matches the value in the CnV register.
When a channel is initially configured to output compare mode, the channel output
updates with its negated value (logic 0 for set/toggle/pulse high and logic one for clear/
pulse low).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (TPM counter = CnV).
Functional Description
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
426
Freescale Semiconductor, Inc.
