27.4.9 Reset Overview
The TPM is reset whenever any chip reset occurs.
When the TPM exits from reset:
• the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] =
0:0);
• the timer overflow interrupt is zero;
• the channels interrupts are zero;
• the channels are in input capture mode;
• the channels outputs are zero;
• the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0).
27.4.10 TPM Interrupts
This section describes TPM interrupts.
27.4.10.1 Timer Overflow Interrupt
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1).
27.4.10.2 Channel (n) Interrupt
The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1).
Functional Description
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
432
Freescale Semiconductor, Inc.
