31.2.2 UART Baud Rate Register Low (UARTx_BDL)
This register, along with UART_BDH, control the prescale divisor for UART baud rate
generation. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when the
transmitter and receiver are both disabled.
UART_BDL is reset to a non-zero value, so after reset the baud rate generator remains
disabled until the first time the receiver or transmitter is enabled; that is, UART_C2[RE]
or UART_C2[TE] bits are written to 1.
Address: 4006_A000h base + 1h offset = 4006_A001h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
1
0
0
UARTx_BDL field descriptions
Field
Description
SBR
Baud Rate Modulo Divisor
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the baud
rate generator. When BR is 1 - 8191, the baud rate equals baud clock/((OSR+1) × BR).
31.2.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system. This
register should only be altered when the transmitter and receiver are both disabled.
Address: 4006_A000h base + 2h offset = 4006_A002h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_C1 field descriptions
Field
Description
7
LOOPS
Loop Mode Select
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the
transmitter output is internally connected to the receiver input.
Table continues on the next page...
Register definition
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
500
Freescale Semiconductor, Inc.
