UARTx_S2 field descriptions (continued)
Field
Description
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the
start bit is identified as bit0.
1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the
setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as
bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].
4
RXINV
Receive Data Inversion
Setting this bit reverses the polarity of the received data input.
NOTE: Setting RXINV inverts the UART_RXD input for all cases: data bits, start and stop bits, break, and
idle.
0
Receive data not inverted.
1
Receive data inverted.
3
RWUID
Receive Wake Up Idle Detect
RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. This bit should
only be changed when the receiver is disabled.
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
character.
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2
BRK13
Break Character Generation Length
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by
the state of this bit. This bit should only be changed when the transmitter is disabled.
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
1
LBKDE
LIN Break Detection Enable
LBKDE selects a longer break character detection length. While LBKDE is set, framing error (FE) and
receive data register full (RDRF) flags are prevented from setting.
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M
= 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or
M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
0
RAF
Receiver Active Flag
RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared
automatically when the receiver detects an idle line.
0
UART receiver idle waiting for a start bit.
1
UART receiver active ( UART_RXD input not idle).
Register definition
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
506
Freescale Semiconductor, Inc.
