the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action
queues an idle character to be sent as soon as the shifter is available. As long as the
character in the shifter does not finish whileUART_C2[TE] is cleared, the UART
transmitter never actually releases control of the UART_TX pin.
The length of the break character is affected by the UART_S2[BRK13], UART_C1[M]
and UART_C4[M10] bits as shown below.
Table 31-27. Break character length
BRK13
M
M10
SBNS
Break character
length
0
0
0
0
10 bit times
0
0
0
1
11 bit times
0
1
0
0
11 bit times
0
1
0
1
12 bit times
0
X
1
0
12 bit times
0
X
1
1
13 bit times
1
0
0
0
13 bit times
1
0
0
1
14 bit times
1
1
0
0
14 bit times
1
1
0
1
15 bit times
1
X
1
0
15 bit times
1
X
1
1
16 bit times
31.3.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional
description. Next, the data sampling technique used to reconstruct receiver data is
described in more detail. Finally, two variations of the receiver wakeup function are
explained.
The receiver input is inverted by setting UART_S2[RXINV]. The receiver is enabled by
setting the UART_C2[RE] bit. Character frames consist of a start bit of logic 0, eight to
ten data bits (msb or lsb first), and one or two stop bits of logic 1. For information about
9-bit or 10-bit data mode, refer to
8-bit, 9-bit and 10-bit data modes
. For the remainder of
this discussion, assume the UART is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register
is not already full, the data character is transferred to the receive data register and the
receive data register full (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] was
already set indicating the receive data register (buffer) was already full, the overrun (OR)
Functional description
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
514
Freescale Semiconductor, Inc.
