32.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin
is configured for a digital function and the corresponding Port Control and Interrupt
module is enabled.
32.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
If
Then
A pin is configured for the GPIO function and the
corresponding port data direction register bit is clear.
The pin is configured as an input.
A pin is configured for the GPIO function and the
corresponding port data direction register bit is set.
The pin is configured as an output and and the logic state of
the pin is equal to the corresponding port data output register.
To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin
data clear, and pin data toggle registers exist to allow one or more outputs within one port
to be set, cleared, or toggled from a single register write.
The corresponding Port Control and Interrupt module does not need to be enabled to
update the state of the port data direction registers and port data output registers including
the set/clear/toggle registers.
32.4.3 IOPORT
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from
address 0xF800_0000. Accesses via the IOPORT interface occur in parallel with any
instruction fetches and will therefore complete in a single cycle.
During Compute Operation, the GPIO registers remain accessible via the IOPORT
interface only. Since the clocks to the Port Control and Interrupt modules are disabled
during Compute Operation, the Pin Data Input Registers do not update with the current
state of the pins.
Chapter 32 General-Purpose Input/Output (GPIO)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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