Signal multiplexing
Register
access
Peripheral
bridge
Module signals
2
I C
Figure 3-23. I2C configuration
Table 3-35. Reference links to related information
Topic
Related module
Reference
Full description
I
2
C
System memory map
—
Clocking
—
Power management
—
Signal multiplexing
Port control
3.9.2.1 IIC instantiation information
This device has two IIC modules. IIC0 is clocked by the bus clock and IIC1 is clocked by
the system clock. Clocking IIC1 at the faster system clock is needed to support standard
IIC communication rates of 100 kbit/s in VLPR mode.
When the package pins associated with IIC have their mux select configured for IIC
operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration.
The digital glitch filter implemented in the IIC0 module, controlled by the
I2C0_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in
bus clock cycle counts.
The digital glitch filter implemented in the IIC1 module, controlled by the
I2C1_FLT[FLT] registers, is clocked from the system clock and thus has filter
granularity in system clock cycle counts.
3.9.3 UART configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Communication interfaces
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
72
Freescale Semiconductor, Inc.
