• A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. The AIPS controller generates unique module enables for all 96
spaces.
• The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO
module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly
interfaced to the core and provides direct access without incurring wait states
associated with accesses via the AIPS controller.
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.6.1 Read-after-write sequence and required serialization of
memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
4.6.2 Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments
System 32-bit base address
Slot
number
Module
0x4000_0000
0
—
0x4000_1000
1
—
0x4000_2000
2
—
0x4000_3000
3
—
Table continues on the next page...
Peripheral bridge (AIPS-Lite) memory map
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
80
Freescale Semiconductor, Inc.
