6.2.2.4 Multipurpose clock generator loss-of-clock (LOC)
The MCG module supports an external reference clock.
If MCG_C6[CME] is set, the clock monitor is enabled. If the external reference falls
below f
loc_low
or f
loc_high
, as controlled by MCG_C2[RANGE], the MCU resets.
RCM_SRS0[LOC] is set to indicate this reset source.
NOTE
To prevent unexpected loss of clock reset events, all clock
monitors must be disabled before entering any low-power
modes, including VLPR and VLPW.
6.2.2.5 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter Stop mode or Compute Operation, but
not all modules acknowledge Stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
6.2.2.6 Software reset (SW)
The SYSRESETREQ field in the NVIC Application Interrupt and Reset Control register
can be set to force a software reset on the device. (See ARM's NVIC documentation for
the full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes
RCM_SRS1[SW] to set.
6.2.2.7 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes RCM_SRS1[LOCKUP] to
set.
Reset
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
98
Freescale Semiconductor, Inc.
