Freescale Semiconductor M54455EVB, User Manual

Page 1: ...MCF54455 Reference Manual M54455EVB Quick Start Guide M54455EVB Schematics MC34702 Switch Mode with Linear Power Supply Datasheet 1 Introduction 1 2 Overview 2 2 1 MCF54455 Overview 2 2 2 M54455EVB Overview 4 2 3 Memory Map Overview 6 2 4 I O Back Panel 7 3 Installation and Configuration 7 4 Hardware Submodules 8 4 1 DDR SDRAM Interface 9 4 2 Reset Controller 9 4 3 MCF5445x Boot Options 9 4 4 Syst...

Page 2: ...S 266 MHz 16 KBytes instruction cache and 16 KBytes data cache 32 Kbytes internal SRAM Support for booting from SPI compatible flash EEPROM and FRAM devices Crossbar switch technology XBS for concurrent access to peripherals or RAM from multiple bus masters 16 channel DMA controller 16 bit 133MHz DDR mobile DDR DDR2 Controller USB 2 0 On the Go controller with ULPI support 32 bit PCI controller 66...

Page 3: ...ntroller GPIO General Purpose Input Output I2 C Inter Integrated Circuit INTC Interrupt controller JTAG Joint Test Action Group interface MMU Memory management unit PCI Peripheral Component Interconnect PIT Programmable interrupt timers PLL Phase locked loop module RNG Random Number Generator RTC Real time clock SSI Synchronous Serial Interface USB OTG Universal Serial Bus On the Go controller MCF...

Page 4: ...ctor Audio interface I2 S mode of SSI module connected to audio codec Multiple USB interface options FS LS Host via on chip transceiver with host support Type A receptacle HS FS LS dual role via external ULPI PHY Mini AB receptacle Two RS232 serial ports RS232 transceivers on UART0 UART1 One USB serial port UART0 serial converted to USB converted on UART0 Built in P E Micro USB Multilink debug int...

Page 5: ...es for RS232 RS232 to USB DSPI I2C Timers etc SSI Audio Interface USB Full speed Interface USB ULPI Interface ULPI Dual FEC PHY RMII mode and 2xRJ45 w integrated magnetics and LEDs FEC0 RMII FEC1 RMII ATA_DATA 8 15 ATA ATA_DATA 15 8 ATA_DATA 7 0 Control Serial I O Interrupts Timers etc DDR2 Parallel Termination VTT VREF DDR2 4 x 512Kbit 64M8 Serial Flash Reset Configuration Latch BDM JTAG 26 pin C...

Page 6: ...xbus Flash1 0x0000_0000 0x00FF_FFFF 16 MB Flexbus Flash0 0x0400_0000 0x0407_FFFF 512 KB Flexbus CPLD1 1 The CPLD and FPGA sections contain details on the memory mapped registers within these address spaces 0x0800_0000 0x08FF_FFFF 16 MB Flexbus FPGA MRAM1 0x0900_0000 0x09FF_FFFF 16 MB DDR2 SDRAM 0x4000_0000 0x4FFF_FFFF 256 MB MCF5445x Internal SRAM 0x8000_0000 0x8000_7FFF 32 KB ATA 0x9000_0000 0x9F...

Page 7: ...quired to interact with the serial port Alternately a USB cable can be used if the USB serial port is configured for use refer to Section 4 17 Serial Ports for details The basic installation steps are as follows 1 Plug in the case s power supply with the power cable provided 2 Connect one end of the provided serial cable to the DB9 serial port connector labelled UART0 Refer to Figure 4 3 Connect t...

Page 8: ...nux is started A network connection is required for the web server portion of the demo to work 7 Plug one end of the provided Ethernet cable into a network or host PC with a DHCP server running Plug the other end of the cable into the FEC0 interface bottom RJ45 receptacle of the M54455EVB 8 To boot Linux issue the following U Boot command bootm 0 9 The demo application prints out a banner message ...

Page 9: ...Xilinx XC95144XL CPLD The CPLD controls the state of the system reset signal SYSRESET gathers reset information from a pushbutton reset SW2 the BDM interface and the FPGA FPGA_DONE At system power on the CPLD holds SYSRESET asserted until the FPGA has loaded its image from the platform flash PROM and asserted the FPGA_DONE signal After system power on the CPLD asserts SYSRESET when it detects the ...

Page 10: ...oot PLL enabled PCI host mode 66MHz PCI slew rate mode PLL multiplier fVCO 6 fREF 4 3 2 Parallel Configuration SW1 2 1 OFF ON If the BOOTMOD pins are 10 during reset the MCF5445x configuration after reset is determined according to the levels driven onto the FB_AD 7 0 pins On the M54455EVB the FB_AD 7 0 pins are actively driven by an 8 bit buffer enabled when the MCF5445x RSTOUT signal is asserted...

Page 11: ...FF OFF ON No PCI non muxed FB addr data 8 bit boot OFF OFF OFF No PCI non muxed FB addr data 32 bit boot Output Clocks SW3 5 PLL Mode ON Limp mode OFF PLL mode none SW3 4 PCI Host Agent Mode when in a PCI mode ON PCI host mode OFF PCI agent mode none SW3 4 Oscillator Mode when in a No PCI mode ON Oscillator bypass mode OFF Crystal oscillator mode PCI_ SW3 3 PCI Slew Rate Mode when in a PCI mode ON...

Page 12: ...ogrammed prior to assembly on the M54455EVB PCB There is an I2C interface on this device that allows it to be reprogrammed However these settings are not retained following a power on reset The state of the CY22393 s S2 frequency control input pin is controlled by a jumper H4 3 4 and the system FPGA signal CLK_GEN_S2 The FPGA uses two conditions to determine how to drive the CLK_GEN_S2 signal the ...

Page 13: ...sulting S2 Value CPU input and PCI Bus Speed 0 0 33 MHz 01 1 Indicates the default values 01 33 MHz1 Jumper Shunt ON 0 33 MHz 11 1 Jumper Shunt OFF1 1 66 MHz Table 6 Clock Generator Outputs Clock CY22393 Output S2 Value Default Clock Frequency MHz Description MCF5445x Input Clock CLKA 0 33 Clock driven into the EXTAL pin on the MCF5445x This is the operating frequency in limp mode and the PLL refe...

Page 14: ... contains the U Boot bootloader The larger of the two flashes is a 16 MByte 8 bit wide 28F128J3D or compatible device referred to as Flash1 By default this flash device is programmed with a Linux image but it can be reprogrammed and used as a boot device if desired The selection of a boot flash device is achieved with a CPLD mode switch setting specifically CPLD_MODE2 which is controllable by DIP ...

Page 15: ...CI timings The M54455EVB is designed to support 33 and 66 MHz 32 bit PCI cards However the speed of the PCI clocks and input clock is limited to that of the slowest device by logic on the M54455EVB The frequency of these clocks is controlled by an input S2 into the clock generator logic The FPGA automatically adjusts this control signal based on the M66EN signal from each PCI slot The S2 signal is...

Page 16: ...CI arbitration signals to the FPGA It would then be left to you to implement an external arbitration scheme in the FPGA The following figures describe how to alter the M54455EVB to route the PCI arbitration signals to the FPGA Reference designators for the cut trace board footprints are CT1 CT10 CT1 CT2 CT5 CT7 and CT9 can be found near the PCI slots J14 J15 J16 J17 and CT8 CT10 CT3 and CT4 can be...

Page 17: ...M54455EVB User s Manual Rev 4 Freescale Semiconductor 17 Figure 7 PCI Request 1 and Request 2 Cut Trace Option Use FPGA for Arbitration Figure 8 PCI Request 3 Cut Trace Option Use FPGA for Arbitration ...

Page 18: ...M54455EVB User s Manual Rev 4 18 Freescale Semiconductor Figure 9 PCI Grant 0 Cut Trace Option Use FPGA for Arbitration Figure 10 PCI Grant 1 Cut Trace Option Use FPGA for Arbitration ...

Page 19: ...roller 4 8 Audio A stereo audio codec is connected to the MCF5445x s SSI interface The SSI operates in I2 S mode to transfer audio data to and from a TLV320AIC23B device The codec s control communications SPI channel is accessed through the MCF5445x s DSPI interface using DSPI_PCS5 The line in line out and microphone inputs of the codec are brought to a 3 5 mm triple audio connector with PC 99 sta...

Page 20: ...own below The TCLK and PSTCLK signals are the only two multiplexed signals that switch input output state depending on which debug mode is selected In BDM mode the PSTCLK is an output from the MCF5445x to the external BDM control interface In JTAG mode TCLK is the test clock input The standard 26 pin BDM header defines pin 24 as PSTCLK A common practice is to place TCLK on pin 6 of this header JP9...

Page 21: ...rol signal When the on chip FS LS transceiver is used the ULPI PHY can be put into its reset state Refer to Section 4 14 CPLD for details 4 10 2 ULPI PHY The ULPI interface of the MCF5445x is also featured on the M54455EVB An external ULPI physical layer device the SMSC USB3300 U927 connects directly to the MCF5445x ULPI interface The USB signals from the ULPI PHY are brought out to a mini AB USB ...

Page 22: ...s a Xilinx Spartan 3 FPGA that provides interrupt control for the four PCI slots and the pushbuttons SW6 and SW7 It also provides a buffered FlexBus interface to the external 256K 16bit MRAM and an interface to a seven segment display and two LEDs 4 13 1 FPGA Registers The FPGA implements several FlexBus accessible memory mapped registers Table 12 shows the memory map and the following sections pr...

Page 23: ...nterrupt is enabled 0 SW6 interrupt source does not assert an IRQ 3 0 PCI Setting these bits allow the corresponding PCI interrupt source to be passed through to the IRQ line determined by FPGA_IRQROUTE 1 Corresponding PCI interrupt is enabled 0 Corresponding PCI interrupt source does not assert an IRQ Address 0x0900_0004 FPGA_IRQSTATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 24: ...S2 State of the S2 control input to the CY22393 clock generator For the S2 pin to assert M66EN must be set the jumper across pins 3 and 4 on H4 must be removed and CLKGENS2EN must be set 0 Input clock and PCI clocks are operating at 33MHz 1 Input clock and PCI clocks are operating at 66MHz 0 CLKGENS2EN Assert the S2 control input to the CY22393 clock generator If the M66EN pin is pulled low this b...

Page 25: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BUILD_WW 0 0 0 0 0 0 0 0 MAJOR_REV MINOR_REV W Reset 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 Figure 16 FPGA Version Register Table 17 FPGA_VERSION Field Descriptions Field Description 31 24 BUILD_WW Build date work week 23 16 Reserved must be cleared 15 8 MAJOR_REV Major revision number Example Revision 1 2 of the FPGA code MAJOR_REV 0x01 M...

Page 26: ... 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 FPGA_7SEGMENT Register Table 18 FPGA_7SEGMENT Field Descriptions Field Description 31 8 Reserved must be cleared 7 0 LED Indicates the hex number you want to display on the 7 segment LED display U28 on the EVB Address 0x0900_0018 FPGA_LEDS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 27: ... boot configuration options Section 4 3 MCF5445x Boot Options provides detailed information on the available boot options 4 14 1 2 Boot Flash Selection The CPLD determines how to route Flexbus chip selects FB_CS0 and FB_CS1 to the two flash devices The flash connected to FB_CS0 is the boot device Refer to Section 4 6 Flash for more information Table 20 CPLD Mode Configuration Switch SW1 Switches D...

Page 28: ...e ATA level shifting buffer is controlled by the CPLD output signal ATA_ENABLE When this signal is asserted the multiplexed ATA FEC1 signals from the MCF5445x is enabled to from the 40 pin ATA connector The FEC1 port of the dual port 10 100 Mbps Ethernet PHY is powered down when the PHY1_PWRDN signal is asserted by the CPLD The ATA_DATA11 pin is multiplexed with the FEC1_RMII_REF_CLK clock This cl...

Page 29: ...ted at the time of assembly These resistors connections input to the CPLD and the values can be read from CPLD_VERSION register Refer to the description of the CPLD registers below Table 24 ATA FEC1 Selection SW1 5 Meaning OFF Full ATA bus enabled ATA_ENABLE asserted driven low PHY1 powered down PHY1_PWRDN asserted driven low RMIICLK2 is disabled RMIICLK2_EN deasserted driven low ON Upper 8 bits o...

Page 30: ...ction 4 14 3 1 30 0x0800_0001 CPLD control register CPLD_CONTROL 8 R W See Section 4 14 3 2 31 0x0800_0002 CPLD on die termination register CPLD_SDODT 8 R W 0x00 4 14 3 3 31 0x0800_0003 CPLD mode register CPLD_MODE 8 R CPLD_MODE 4 14 3 4 32 0x0800_0004 CPLD flash configuration register CPLD_FLASHCFG 8 R W 0x01 4 14 3 5 32 0x0800_0005 CPLD LED control register CPLD_LEDS 8 R W 0x00 4 14 3 6 33 Addre...

Page 31: ...n 7 3 Reserved must be cleared 2 FEC0 FEC0 PHY mode 0 FEC0 Ethernet PHY in normal functional mode 1 FEC0 Ethernet PHY in power down mode 1 ATA ATA and FEC1 PHY mode 0 Full ATA data bus enabled FEC1 PHY in power down mode 1 Upper 8 bits of ATA data bus disabled FEC1 PHY in normal functional mode 0 ULPI ULPI PHY mode 0 ULPI PHY in normal functional mode 1 ULPI PHY held in reset state Address 0x0800_...

Page 32: ...DE Field Descriptions Field Description 7 0 CPLD_ MODE Status of the CPLD_MODE 7 0 signals which are controllable via the SW1 switch 0 Corresponding SW1 switch is in the ON position 1 Corresponding SW1 switch is in the OFF position Address 0x0800_0004 CPLD_FLASHCFG 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 FLASH_WP W Reset 0 0 0 0 0 0 0 1 Figure 23 CPLD_FLASHCFG Register Table 32 CPLD_FLASHCFG Field Descrip...

Page 33: ...faces and timers that are not made available via dedicated interfaces on the M54455EVB However these interfaces and others are brought out to a general purpose header J908 for easy access The following interfaces are accessible on J908 DSPI I2 C DMA external request acknowledge DMA timer input output UART0 UART1 Table 34 shows the signal assignments on J908 Address 0x0800_0005 CPLD_LEDS 7 6 5 4 3 ...

Page 34: ... connector can interface with a host PC instead of the standard RS232 connector A custom virtual COMM port driver may be required on the host PC and can be found here http www silabs com tgwWebApp public web_content products Microcontrollers USB en mcu _vcp htm Table 34 J908 Signal Assignments Signal Name Pin Signal Name VDD 1 2 GND VDD 3 4 GND U1CTS 5 6 U0TXD U1RTS 7 8 U0RXD U1RXD 9 10 U0RTS U1TX...

Page 35: ...evices on the board with the exception of the PCI slots The regulators generate these voltages from a 5 V external supply The 5 V supply can be provided through one of the following the ATX power connector a barrel jack connector or a 6 pin molex power connector to a lab grade regulated supply Jumpers are provided that allow for the 3 3 and 1 5 V supplies to be separated from the MCF5445x The inte...

Page 36: ...ontrol signals OFF Disable UART1 flow control signals JP903 1 2 Boot into JTAG mode 2 32 Boot into BDM mode JP904 1 22 Connect BDM pin 24 to MCF5445x TCLK_PSTCLK 2 3 Connect BDM pin 6 to MCF5445x TCLK_PSTCLK JP909 JP910 JP911 JP912 1 2 Connect UART0 signals to DB9 interface 2 32 Connect UART0 signals to USB interface JP918 1 22 Connect MCF5445x USBCLKIN to CLKOUT of USB3300 2 3 Connect MCF5445x US...

Page 37: ...ault uses the ATX power supply J50 J24 BDM JTAG connector J909 Serial interface breakout J910 SSI interface signals Table 37 Switches Reference Designator Function SW1 CPLD_MODE switch See Section 4 14 CPLD for more information SW2 Board reset push button SW3 Parallel configuration switch See Section 4 3 MCF5445x Boot Options for details SW4 ATX power ON OFF button SW5 FPGA_CFG switch Not used at ...

Page 38: ...nd specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by custome...