M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor
9
4.1
DDR SDRAM Interface
The MCF5445
x
DDR SDRAM controller has the following features:
•
Supports a glueless interface to DDR, DDR2, and mobile/low-power DDR SDRAM devices
•
Support for 16-bit fixed memory port width
•
16-byte critical word first burst transfer
•
Up to 14 lines of row address, up to 11 column address lines, 2 bits of bank address, and two chip
selects.
•
Supports up to 512 MByte of memory; minimum memory configuration of 8 MByte
•
Supports page mode to maximize the data rate
•
Supports sleep mode and self-refresh mode
The M54455EVB features 256 MBytes of DDR2 SDRAM. Four 8-bit wide Micron MT47H64M8
(512 Mbit) devices are arranged as two 16 M
×
8
×
4 banks per SDRAM controller chip select. This results
in two 16-bit wide, 128 MBytes blocks of DDR2 memory
The SDRAM interface is terminated with parallel termination resistors. The MCF5445
x
does not provide
control for the DDR2 on-die termination. The ODT pins on the DDR2 devices are connected to control
signals from the CPLD for test purposes only. These signals are disabled in the normal functional mode.
4.2
Reset Controller
The reset controller on the M54455EVB is implemented in a Xilinx XC95144XL CPLD. The CPLD
controls the state of the system reset signal (SYSRESET) gathers reset information from a pushbutton reset
(SW2), the BDM interface, and the FPGA (FPGA_DONE). At system power-on, the CPLD holds
SYSRESET asserted until the FPGA has loaded its image from the platform flash PROM and asserted the
FPGA_DONE signal. After system power-on, the CPLD asserts SYSRESET when it detects the assertion
of any of the reset sources.
4.3
MCF5445x Boot Options
During a system reset, the CPLD also drives the boot mode configuration signals into the MCF5445
x
. The
MCF5445
x
has three boot mode options:
•
Boot with default configuration constants specified in the RCON register,
•
Boot with configuration data specified by the Flexbus FB_AD[7:0] pins, and
•
Boot with configuration data obtained from an external SPI memory through the serial boot
facility.
In all of these cases, the boot code is fetched from an external memory connected to the Flexbus on
FB_CS0 with the possible exception of the serial boot mode. In serial boot mode, if the boot load length
field (BLL) in the reset configuration data stored in the SPI memory is non-zero, then boot code is loaded
from the SPI memory instead of from Flexbus.
The MCF5445
x
boot mode is determined by the state of the BOOTMOD[1:0] input pins during the rising
edge of RSTOUT (MCF5445
x
reset output signal). The CPLD drives BOOTMOD[1:0] to the values that
