M68HC08RG/AD
10
M68HC08 Family Reference Guide
MOTOROLA
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator
A
←
(A
⊕
M)
0
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M
←
(M) + $01
A
←
(A) + $01
X
←
(X) + $01
M
←
(M) + $01
M
←
(M) + $01
M
←
(M) + $01
–
–
–
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump
PC
←
Jump Address
–
–
–
–
–
–
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC
←
(PC) + n (n = 1, 2, or 3)
Push (PCL); SP
←
(SP) – $0001
Push (PCH); SP
←
(SP) – $0001
PC
←
Unconditional Address
–
–
–
–
–
–
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory
A
←
(M)
0
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LDHX #opr
LDHX opr
Load Index Register (H:X)
from Memory
H:X
← (
M:M
+ $0001
)
0
–
–
–
IMM
DIR
45
55
ii
jj
dd
3
4
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory
X
←
(M)
0
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
– –
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
Table 2. Instruction Set Summary (Sheet 5 of 8)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
M
ode
Opc
o
de
O
p
erand
Cycl
es
V H I N Z C
C
b0
b7
0
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
