TIME PROCESSOR UNIT
MC68332
7-2
USER’S MANUAL
7.2 TPU Components
The TPU module consists of two 16-bit time bases, sixteen independent timer chan-
nels, a task scheduler, a microengine, and a host interface. In addition, a dual-port pa-
rameter RAM is used to pass parameters between the module and the host CPU.
7.2.1 Time Bases
Two 16-bit counters provide reference time bases for all output compare and input
capture events. Prescalers for both time bases are controlled by the host CPU via bit
fields in the TPU module configuration register (TPUMCR). Timer count registers
TCR1 and TCR2 provide access to current counter values. TCR1 and TCR2 can be
read or written to by TPU microcode, but are not directly available to the host CPU.
The TCR1 clock is derived from the system clock. The TCR2 clock can be derived from
the system clock or from an external clock input via the T2CLK pin.
7.2.2 Timer Channels
The TPU has 16 independent channels, each connected to an MCU pin. The channels
have identical hardware. Each channel consists of an event register and pin control
logic. The event register contains a 16-bit capture register, a 16-bit compare/match
register, and a 16-bit greater-than-or-equal-to comparator. The direction of each pin,
either output or input, is determined by the TPU microengine. Each channel can either
use the same time base for match and capture, or can use one time base for match
and the other for capture.
7.2.3 Scheduler
When a service request is received, the scheduler determines which TPU channel is
serviced by the microengine. A channel can request service for one of four reasons:
for host service, for a link to another channel, for a match event, or for a capture event.
The host system assigns each active channel one of three priorities: high, middle, or
low. When multiple service requests are received simultaneously, a priority-scheduling
mechanism grants service based on channel number and assigned priority.
7.2.4 Microengine
The microengine is composed of a control store and an execution unit. Control-store
ROM holds the microcode for each factory-masked time function. When assigned to a
channel by the scheduler, the execution unit executes microcode for a function as-
signed to that channel by the host CPU. Microcode can also be executed from the
TPURAM module instead of the control store. The TPURAM module allows emulation
and development of custom TPU microcode without the generation of a microcode
ROM mask. Refer to
for more information.
7.2.5 Host Interface
Host interface registers allow communication between the host CPU and the TPU,
both before and during execution of a time function. The registers are accessible from
the IMB through the TPU bus interface unit. Refer to
and
for register bit/field definitions and address
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
