MC68332
ELECTRICAL CHARACTERISTICS
USER’S MANUAL
A-13
Notes for Tables A–6 and A–6a:
1.All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2.Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
3.When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum al-
lowable t
Xcyc
period is reduced when the duty cycle of the external clock signal varies. The relationship between
external clock input duty cycle and minimum t
Xcyc
is expressed:
Minimum t
Xcyc
period = minimum t
XCHL
/ (50% – external clock input duty cycle tolerance).
4.Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference sig-
nal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
5.Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside
the limits shown in specification 9.
6.If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification be-
tween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
7.Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
8.Maximum value is equal to (t
cyc
/ 2) + 25 ns.
9.If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup
time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
10. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cy-
cles of the current operand transfer are complete and RMC is negated.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification
47A).
12. After external RESET negation is detected, a short transition period (approximately 2 t
cyc
) elapses, then the SIM
drives RESET low for 512 t
cyc
.
13.External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset
is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Address access time = (2.5 + WS) t
cyc
– t
CHAV
– t
DICL
Chip select access time = (2 + WS) t
cyc
– t
CLSA
– t
DICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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