REGISTER SUMMARY
MC68332
D-6
USER’S MANUAL
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the
user or supervisor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
access only.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to
prevent SIM interrupts from being discarded during initialization.
D.2.2 SIMTR
— System Integration Test Register
$YFFA02
SIMTR is used for factory test only.
D.2.3 SYNCR
— Clock Synthesizer Control Register
$YFFA04
SYNCR determines system clock operating frequency and mode of operation. Clock
frequency is determined by SYNCR bit settings as follows:
W — Frequency Control (VCO)
0 = Base VCO frequency
1 = VCO frequency multiplied by four
X — Frequency Control Bit (Prescale)
0 = VCO frequency divided by four (base system clock frequency)
1 = VCO frequency divided by two (system clock frequency doubles)
Y[5:0] — Frequency Control (Counter)
The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-
back loop. Values range from 0 to 63.
EDIV — ECLK Divide Rate
0 = ECLK is system clock divided by 8
1 = ECLK is system clock divided by 16
SLIMP — Limp Mode
0 = External crystal is VCO reference
1 = Loss of crystal reference
SLOCK — Synthesizer Lock
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or system clock is external.
15
14
13
8
7
6
5
4
3
2
1
0
W
X
Y
EDIV
0
0
SLIMP
SLOCK RSTEN
STSIM
STEXT
RESET:
0
0
1
1
1
1
1
1
0
0
0
U
U
0
0
0
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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