QUEUED SERIAL MODULE
MC68332
6-18
USER’S MANUAL
The following expressions apply to SCK baud rate:
or
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state value.
The DSCK field in command RAM determines the delay period from chip-select asser-
tion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines
the period of delay before the assertion of SCK. The following expression determines
the actual delay before SCK:
where DSCKL equals {1, 2, 3,..., 127}.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the DSCK period.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value of eight to sixteen bits, inclusive. The programmed value
must be written into the BITS field in SPCR0. The BITSE field in command RAM de-
termines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
shows BITS field encoding.
SCK Baud Rate
System Clock
2 SPBR
×
------------------------------------
=
SPBR
System Clock
2 SCK
×
(
)
Baud Rate Desired
(
)
----------------------------------------------------------------------------------
=
PCS to SCK Delay
DSCKL
System Clock Frequency
------------------------------------------------------------------
=
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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