SYSTEM INTEGRATION MODULE
MC68332
4-4
USER’S MANUAL
terrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized,
the CPU32 processes a spurious interrupt exception.
Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all
other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to
for a discussion of interrupt arbitration.
4.2.3 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in the SIMCR determines what the external bus interface does during internal transfer
operations.
shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to
for more information.
4.2.4 Factory Test Mode
The internal IMB can serve as slave to an external master for direct module testing.
This test mode is reserved for factory test. Slave mode is enabled by holding DATA11
low during reset. The slave enabled (SLVEN) bit is a read-only bit that shows the reset
state of DATA11.
4.2.5 Register Access
The CPU32 can operate at either of two privilege levels. Supervisor level is more priv-
ileged than user level — all instructions and system resources are available at super-
visor level, but access is restricted at user level. Effective use of privilege level can
protect system resources from uncontrolled access. The state of the S bit in the CPU
status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, reg-
isters with controlled access are restricted to supervisor access only.
4.2.6 Reset Status
The reset status register (RSR) latches internal MCU status during reset. Refer to
for more information.
Table 4-1 Show Cycle Enable Bits
SHEN
Action
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
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Freescale Semiconductor, Inc.
For More Information On This Product,
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