MC68332
SYSTEM INTEGRATION MODULE
USER’S MANUAL
4-9
4.2.13 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in-
ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt
timer are affected. The halt monitor and spurious interrupt monitor continue to operate
normally. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus
monitor when FREEZE is asserted, and setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted. When FRZSW is set, FREEZE assertion must be at least two
times the PIT clock source period to ensure an accurate number of PIT counts.
4.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
support changes in clock rate during operation.
The system clock signal can be generated in one of three ways. An internal phase-
locked loop can synthesize the clock from either an internal reference or an external
reference, or the clock signal can be input from an external frequency source. Keep
these clock sources in mind while reading the rest of this section.
is a block
diagram of the system clock. Refer to
APPENDIX A ELECTRICAL CHARACTERIS-
for clock specifications.
Figure 4-4 System Clock Block Diagram
32 PLL BLOCK
CLKOUT
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
CRYSTAL
OSCILLATOR
SYSTEM
CLOCK
SYSTEM CLOCK CONTROL
FEEDBACK DIVIDER
W
X
Y
EXTAL
XTAL
XFC
V
DDSYN
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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