MC68332
SYSTEM INTEGRATION MODULE
USER’S MANUAL
4-11
ply must be used as the V
DDSYN
source. Adequate external bypass capacitors should
be placed as close as possible to the V
DDSYN
pin to assure stable operating frequen-
cy. When an external system clock signal is applied and the PLL is disabled, V
DDSYN
should be connected to the V
DD
supply. Refer to the
SIM Reference Manual (SIMRM/
AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain
a 50% clock duty cycle, VCO frequency is either two or four times system clock fre-
quency, depending on the state of the X bit in SYNCR. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a
phase comparator. The other phase comparator input is a reference signal, either from
the crystal oscillator or from an external source. The comparator generates a control
signal proportional to the difference in phase between the two inputs. The signal is low-
pass filtered and used to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock
stability.
shows two recommended filters. XFC pin leakage must be as
specified in
APPENDIX A ELECTRICAL CHARACTERISTICS
stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled. The XFC pin must be left float-
ing in this case.
Figure 4-6 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time
is affected by the filter time constant and by the amount of difference between the two
comparator inputs. Whenever comparator input changes, the synthesizer must relock.
Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does
not come out of reset state until the synthesizer locks. Crystal type, characteristic fre-
quency, and layout of external oscillator circuitry affect lock time.
16/32 XFC CONN
1. Maintain low-leakage on the XFC node. See Appendix A electrical characteristics for more information.
2. Recommended loop filter for reduced sensitivity to low-frequency noise.
0.01
µ
F
0.1
µ
F
NORMAL OPERATING
ENVIRONMENT
HIGH-STABILITY OPERATING
ENVIRONMENT
C4
C1
V
SSI
V
DDSYN
XFC
1
0.1
µ
F
C3
0.01
µ
F
0.1
µ
F
C4
C1
V
SSI
V
DDSYN
XFC
1, 2
0.1
µ
F
C3
0.01
µ
F
C2
18k
Ω
R1
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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