SYSTEM INTEGRATION MODULE
MC68332
4-26
USER’S MANUAL
Figure 4-10 Write Cycle Flowchart
4.5.3 Fast Termination Cycles
When an external device has a fast access time, the chip-select circuit fast-termination
option can provide a two-cycle external bus transfer. Because the chip-select circuits
are driven from the system clock, the bus cycle termination is inherently synchronized
with the system clock.
If multiple chip selects are to be used to select the same device that can support fast
termination, and match conditions can occur simultaneously, program the DSACK
field in each associated chip-select option register for fast termination. Alternately, pro-
gram one DSACK field for fast termination and the remaining DSACK fields for exter-
nal termination.
Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
WR CYC FLOW
MCU
PERIPHERAL
ADDRESS DEVICE (S0)
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
ACCEPT DATA (S2 + S3)
3) ASSERT DSACK SIGNALS
TERMINATE CYCLE
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
TERMINATE OUTPUT TRANSFER (S5)
START NEXT CYCLE
ASSERT AS (S1)
PLACE DATA ON DATA[15:0] (S2)
ASSERT DS AND WAIT FOR DSACK (S3)
OPTIONAL STATE (S4)
NO CHANGE
1) NEGATE DSACK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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