MC68332
SYSTEM INTEGRATION MODULE
USER’S MANUAL
4-31
4.5.4.2 LPSTOP Broadcast Cycle
Low-power stop is initiated by the CPU32. Individual modules can be stopped by set-
ting the STOP bits in each module configuration register, or the SIM can turn off sys-
tem clocks after execution of the LPSTOP instruction. When the CPU executes
LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power mode when either an interrupt of higher priority than the stored mask or a
reset occurs. Refer to and
SECTION 5 CENTRAL PROCESSING UNIT
for more in-
formation.
During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address
$3FFFE. This write puts a copy of the interrupt mask value in the clock control logic.
The mask is encoded on the data bus as shown in
. The LPSTOP CPU
space cycle is shown externally (if the bus is available) as an indication to external de-
vices that the MCU is going into low-power stop mode. The SIM provides an internally
generated DSACK response to this cycle. The timing of this bus cycle is the same as
for a fast write cycle.
Figure 4-13 LPSTOP Interrupt Mask Level
4.5.5 Bus Exception Control Cycles
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing oc-
curs when bus cycles are not terminated in the expected manner. The internal bus
monitor can be used to generate BERR internally, causing a bus error exception to be
taken. Bus cycles can also be terminated by assertion of the external BERR or HALT
signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
, which indicates the results of each type of bus cycle ter-
mination.
Normal Termination
DSACK is asserted; BERR and HALT remain negated (case 1).
Halt Termination
HALT is asserted at the same time or before DSACK, and BERR remains negated
(case 2).
Bus Error Termination
BERR is asserted in lieu of, at the same time as, or before DSACK, or after
DSACK, and HALT remains negated; BERR is negated at the same time or after
DSACK.
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IP MASK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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