MC68332
SYSTEM INTEGRATION MODULE
USER’S MANUAL
4-33
4.5.5.1 Bus Errors
The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU detects assertion of the IMB BERR signal (by the internal bus
monitor or an external source) while the HALT signal remains negated.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several fac-
tors:
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
BERR is asserted.
• Whether BERR is asserted during a program space access or a data space ac-
cess.
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
CAUTION
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an in-
struction prefetch, the IMB precharge state (bus pulled high, or $FF)
is latched into the CPU32 instruction register, with indeterminate re-
sults.
4.5.5.2 Double Bus Faults
Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to
SECTION 5 CENTRAL PROCESSING UNIT
for more informa-
tion about exceptions. However, a special case of bus error, called double bus fault,
can abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in two ways:
1. When bus error exception processing begins and a second BERR is detected
before the first instruction of the first exception handler is executed.
2. When one or more bus errors occur before the first instruction after a RESET
exception is executed.
3. A bus error occurs while the CPU32 is loading information from a bus error
stack frame during a return from exception (RTE) instruction.
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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