MC68332
SYSTEM INTEGRATION MODULE
USER’S MANUAL
4-49
B. The processor state is stacked. The S bit in the status register is set, establish-
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]
= %1111, which indicates that the cycle is an interrupt acknowledge CPU
space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of
the interrupt request being acknowledged; and ADDR0 = %1.
3. The request level is latched from the address bus into the interrupt priority
mask field in the status or condition code register.
D. Modules that have requested interrupt service decode the priority value in AD-
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by
IARB contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt moni-
tor asserts BERR, and the CPU generates the spurious interrupt vector
number.
2. The dominant interrupt source supplies a vector number and DSACK sig-
nals appropriate to the access. The CPU acquires the vector number.
3. The AVEC signal is asserted (the signal can be asserted by the dominant
interrupt source or the pin can be tied low), and the CPU generates an au-
tovector number corresponding to interrupt priority.
4. The bus monitor asserts BERR and the CPU32 generates the spurious in-
terrupt vector number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor
transfers control to the exception handler routine.
4.7.5 Interrupt Acknowledge Bus Cycles
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to
and the
SIM Reference Manual (SIMRM/AD).
4.8 Chip Selects
Typical microcontrollers require additional hardware to provide external chip-select
and address decode signals. The MCU includes 12 programmable chip-select circuits
that can provide 2- to 20-clock-cycle access to external memory and peripherals. Ad-
dress block sizes of two Kbytes to one Mbyte can be selected.
gram of a basic system that uses chip selects.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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