SYSTEM INTEGRATION MODULE
MC68332
4-50
USER’S MANUAL
Figure 4-17 Basic MCU System
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, ad-
dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac-
knowledge) to parameters stored in chip-select registers. If all parameters match, the
appropriate chip-select signal is asserted. Select signals are active low. If a chip-select
function is given the same address as a microcontroller module or an internal memory
array, an access to that address goes to the module or array, and the chip-select sig-
nal is not asserted. The external address and data buses do not reflect the internal ac-
cess.
All chip-select circuits are configured for operation out of reset. However, all chip-se-
lect signals except CSBOOT are disabled, and cannot be asserted until the BYTE field
32 EXAMPLE SYS BLOCK
ADDR[23:0]
SIZ
CLKOUT
AS
FC
DSACK
DS
R/W
DATA[15:0]
CS3
CS5
IRQ
CSBOOT
ADDR[15:0]
SIZ
CLK
DSACK
AS
DS
CS
DATA[15:0]
IACK
IRQ
ADDR[23:0]
DATA[15:8]
CS
R/W
MEMORY
ADDR[23:0]
DATA[7:0]
CS
R/W
MEMORY
MCU
ASYNC BUS
PERIPHERAL
1
2
2
2
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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