Device User Guide — 9S12DT128DGV2/D V02.16
123
Freescale Semiconductor
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
C
=10KHz:
The capacitance C
s
can now be calculated as:
The capacitance C
p
should be chosen in the range of:
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in
. With each transition of the clock f
cmp
, the
deviation from the reference clock f
ref
is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
n
f
VCO
f
ref
-------------
2
synr
1
+
(
)
⋅
=
=
= 50
R
2
π
n f
C
⋅ ⋅ ⋅
K
Φ
-----------------------------
=
= 2*
π
*50*10kHz/(316.7Hz/
Ω
)
=9.9k
Ω
=~ 10k
Ω
C
s
2
ζ
2
⋅
π
f
C
R
⋅
⋅
----------------------
0.516
f
C
R
⋅
---------------
ζ
0.9
=
(
)
;
≈
=
= 5.19nF =~ 4.7nF
C
s
20
⁄
C
p
C
s
10
⁄
≤
≤
C
p
= 470pF
Summary of Contents for MC9S12A128
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