Chapter 4 Multiplexed External Bus Interface (MEBIV3)
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
151
Rev 01.24
4.4.2
Stretched Bus Cycles
In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the
HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud
rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block
of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While
stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle,
write data would already be driven onto the data bus so the length of time write data is valid is extended
in the case of a stretched bus cycle. Read data would not be captured by the system until the E clock falling
edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the
falling edge of the stretched E clock. The chip selects, and R/W signals remain valid during the period of
stretching (throughout the stretched E high time).
NOTE
The address portion of the bus cycle is not stretched
.
4.4.3
Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (
). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
0
0
1
16-bit read of an even address
1
1
1
16-bit read of an odd address
(low/high data swapped)
0
0
0
16-bit write to an even address
1
1
0
16-bit write to an odd address
(low/high data swapped)
Table 4-16. Mode Selection
MODC
MODB
MODA
Mode Description
0
0
0
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
0
1
Emulation Expanded Narrow, BDM allowed
0
1
0
Special Test (Expanded Wide), BDM allowed
0
1
1
Emulation Expanded Wide, BDM allowed
1
0
0
Normal Single Chip, BDM allowed
1
0
1
Normal Expanded Narrow, BDM allowed
1
1
0
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
1
1
1
Normal Expanded Wide, BDM allowed
Table 4-15. Access Type vs. Bus Control Pins
LSTRB
AB0
R/W
Type of Access
Summary of Contents for MC9S12C Family
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